Field of the Invention
The present invention relates to a data transfer control device that conducts data transfer between a module, such as an image processing module, and a memory.
Description of the Background Art
A direct memory access (DMA) controller disclosed in Japanese Patent No. 4677581 is an example of a conventional data transfer control device that conducts data transfer between a module, such as an image processing module, and a memory.
The DMA controller disclosed in Japanese Patent No. 4677581 prepares, in four registers, two pairs of a start address and an end address of a main memory. Two selectors perform switching between a start address A of a storage area A of the main memory and a start address B of a storage area B of the main memory, and between an end address A of the storage area A and an end address B of the storage area B. An address counter increases a value of the start address of one of the pairs one by one to generate a destination address, and outputs the destination address to an arbiter. The arbiter controls a memory control circuit so that DMA transfer is conducted with respect to the destination address of the main memory. As a result, the DMA controller that reduces a load put on a CPU and improves a DMA transfer rate is provided.
FIG. 8 is a block diagram schematically showing configuration of conventional DMA transfer achieved, for example, by the DMA controller disclosed in Japanese Patent No. 4677581.
As shown in FIG. 8, data transfer between an image processing module 62 (a predetermined module) and a memory 63 is conducted via a DMA controller (DMAC) 61. In this case, a CPU 64 performs pre-setting processing of providing the DMAC 61 with address information indicating details of data transfer between the image processing module 62 and the memory 63 prior to the data transfer between the image processing module 62 and the memory 63 via the DMAC 61 (hereinafter, also simply referred to as “DMA data transfer”). The DMAC 61 controls the DMA data transfer based on the address information.
The address information indicates a storage area to be accessed typically by a start address and an end address (or information on the amount of data to be accessed) of the storage area to be accessed. The storage area, in the memory 63, from the start address to the end address to be accessed is herein referred to as a bank.
FIG. 9 schematically shows a plurality of banks BK0-BK2 in the memory 63. As shown in FIG. 9, the banks BK0-BK2 as storage areas to be accessed in the memory 63 can be designated by setting start addresses BST0-BST2 and end addresses BED0-BED2 as the address information.
When DMA data transfer is conducted in the order of the banks BK0, BK1, and BK2, for example, the CPU 64 performs address pre-setting processing of outputting address information {(BST0, BED0), (BST1, BED1), (BST2, BED2)} to the DMAC 61 prior to the DMA data transfer.
In the above-mentioned case, the DMAC 61 is required to store therein three pieces of address information specifying respective banks (pairs of a start address BSTi (i=0-2) and an end address BEDi), and is thus required to have the same number of storage areas for storing the address information as the number of banks targeted for the DMA data transfer.
Furthermore, a case where the image processing module 62 performs read processing of reading data from the bank BK0, which is accessed first, performs arithmetic processing based on the read data, and determines a start address of the bank BK1, which is accessed next, from the results of the arithmetic processing is considered.
In this case, the CPU 64 is required to perform a first address pre-setting processing of setting address information regarding the bank BK0, and, after DMA data transfer (the read processing performed by the image processing module 62) is conducted with respect to the bank BK0, to perform a second address pre-setting processing of setting address information regarding the bank BK1 based on the results of the arithmetic processing performed by the image processing module 62.
As set forth above, conventional DMA transfer achieved as described above has a problem in that a relatively high load is put on the CPU due to the need for intervention of the CPU.
There is also a problem of an increase in circuit size as the DMA controller is required to include storages for storing therein a plurality of pieces of address information so that the DMA controller can store therein the largest possible number of pieces of address information in order for the CPU to perform address pre-setting processing without any difficulty.